1. Field of the Invention
This invention relates to dynamic RAM (DRAM) to store data in pairs of cells, and particularly to DRAM which, through a twin-cell structure, is able to reduce power consumption, or is able to speed up the operation. In this Specification, such DRAM is referred to as xe2x80x9ctwin-cell DRAM.xe2x80x9d
2. Description of the Related Art
DRAM is large-capacity memory having memory cells consisting of one selection transistor (cell transistor) and one storage capacitor (cell capacitor). It is widely used as the cache memory in computers and in other applications.
In conventional DRAM, by driving a selected word line, the cell transistors connected to the word line are made conducting, cell capacitors are connected to bit lines, the bit line potential is raised or lowered according to whether there is or is not an electric charge on the cell capacitor, and this charge is read by a sense amplifier. Here in order to increase the read sensitivity, another bit line connected to the sense amplifier is used as a reference potential.
That is, in conventional DRAM, data 1""s and 0""s are stored by either accumulating or not accumulating electric charge in a single cell capacitor. This state is reflected in the potential of one bit line, and using the potential of the other bit line as a reference potential, the sense amplifier reads the data stored in the cell.
FIG. 9 is a drawing showing the configuration of conventional DRAM. In FIG. 9, sense amplifier blocks S/A0, S/A1 containing sense amplifier circuits are arranged on both sides of the memory cell array MCA. Within the memory cell array MCA are arranged plural word lines WL0 to WL5, and plural bit lines BL0, /BL0 and BL1, /BL1 intersecting with the former; at the positions of intersection are positioned memory cells MC00, etc. Consisting of a cell transistor and cell capacitor. The bit line pair BL0, /BL0 are connected to the sense amplifier block S/A0, and the bit line pair BL1, /BL1 is connected to the sense amplifier block S/A1.
Within the sense amplifier block S/A1 are provided bit line transfer gates BLT1, /BLT1, a precharge circuit PR1, a sense amplifier circuit SA1, and a column gate CLG. The bit line transfer gates BLT2, /BLT2 are connected to a bit line pair within a memory cell array on the right side, not shown.
Read operations in the conventional DRAM of FIG. 9 are as follows. During the precharge interval, the bit line pair BL1, /BL1 is precharged to a precharge level VBL by activation of an equalizing signal EQ12. This precharge level is normally the voltage Vii/2(Vcc/2) intermediate between the cell voltage and bit line voltage Vii(Vcc) on the H-level side, and the ground voltage on the L-level side. Next, when the word line WL2 is selected and driven, the transistors of the memory cells MC21, MC20 are made conducting, and the potentials of the bit lines BL1, BL0 change according to the cell voltages. The sense amplifier SA1 within the sense amplifier block S/A1 is activated by the activation signals SAE, /SAE, the voltage difference between the bit lines BL1 and /BL1 is detected, and the bit line pair BL1, /BL1 is amplified to either the power source voltage Vii(Vcc) or to ground voltage Vss by the sense amplifier SA1. Finally, the column gate CLG is made conducting by activation of the column select signal CL, and the voltage amplified by the sense amplifier is read to the data bus lines DB, /DB.
Presently the word line WL2 drops, the amplified bit line potential is retained in the memory cell MC21, rewriting is performed, the sense amplifier is deactivated, and bit line precharge is performed.
As described above, in conventional DRAM a data 1 or 0 is stored in a single memory cell, and when the memory cell is selected, the potential of one bit line changes while the potential of the other bit line is used as a reference potential, and the stored data is read by the sense amplifier.
Because of this configuration, conventional DRAM is subject to various constraints. For example, the cell voltage in a memory cell which stores the H level must be kept at a prescribed high-voltage level higher than the reference voltage Vii/2, even when the voltage declines due to a leakage current. If the H-level cell voltage drops below this, the corresponding bit line potential can no longer be raised sufficiently, and detection by the sense amplifier becomes difficult. Hence in conventional DRAM, in order that data reading failure due to leakage current does not occur, refresh operations must be performed at prescribed time intervals.
Further, in conventional DRAM it is desirable that the word line driving potential be set higher than the H-level side cell voltage or bit line voltage by an amount equal to or greater than the cell transistor threshold voltage, in order that the H-level side cell voltage be made sufficiently high. This is because by setting the H-level side cell voltage sufficiently high, the bit line potential can be raised sufficiently during reading, and it becomes possible to read using the sense amplifier. And even if the cell voltage declines due to the leakage current, if the voltage is higher than a prescribed voltage above the bit line precharge level Vii/2, the bit line potential can be raised sufficiently, as described above.
Also, in conventional DRAM, during read operations the word line is driven at a sufficiently high level, and after drawing the charge within the memory cell onto the bit line sufficiently, it is desirable that the sense amplifier be activated. This is because in order to enable detection by the sense amplifier, the bit line potential must be raised sufficiently relative to the cell voltage H level. This operation invites slowing of operations.
The various constraints described above on the frequent refresh operation, on raising the word line to high voltage and on other operations, all invite increases in power consumption. In DRAM devices, large capacities have been achieved through advances in microminiature processing technology, but on the other hand, the drawback of large power consumption accompanying the fact that refresh operations are necessary and other circumstances, has not yet been adequately resolved. Conversely, conventional DRAM has the problem that if power consumption is reduced, operation is slowed.
As a DRAM which resolves the above problems, a twin-cell DRAM device has been proposed in which complementary data is stored in a pair of memory cells, and in reading this pair of memory cells is selected simultaneously, the complementary data read to a bit line pair, and the bit line pair is driven by a sense amplifier. For example, in Japanese Patent Publication No. S54-28252 (Great Britain Patent No. 1502334), Japanese Patent Laid-open No. S55-157194, Japanese Patent Laid-open No. S61-34790, and Japanese Patent Laid-open No. 8-222706 (U.S. Pat. No. 5,661,678) are described configurations for storing a single datum in two memory cells.
However, all of these previous methods merely describe how a single datum is simply stored in a pair of memory cells, complementary data is read to a bit line pair, and driving is performed by a sense amplifier. The twin-cell DRAM of these previous methods do result in larger operating margins for sense amplifiers, and refresh cycles can be lengthen to some extent; but problems remain, including the facts that all sense amplifiers operate simultaneously, and that the operating margin is reduced by crosstalk between neighboring bit lines.
The object of this invention is to provide a DRAM device with a novel structure, with reduced power consumption.
A separate object of this invention is to provide a DRAM device with a novel structure, which is able to lengthen refresh cycles and reduce power consumption.
In order to achieve the above objects, as one aspect of this invention, the DRAM is configured such that data to be stored is stored as complementary data in one pair of memory cells, and this pair of memory cells is connected to one pair of bit lines connected to a common sense amplifier in response to selection of the word line. That is, at the positions of intersection of the pair of bit lines connected to the sense amplifier and the single word line, a pair of memory cells is positioned; by selecting the word line, complementary data is written from the pair of bit lines to the pair of memory cells, or complementary data is read to the pair of bit lines. The H level and L level are stored in the pair of memory cells as one bit of stored data, so that, as explained in the embodiment described below, the read sensitivity is increased, and refresh cycles can be made longer, or the word line driving level can be lowered, or the sense amplifier activation timing can be speeded.
Further, in this invention the bit lines comprising the first bit line pair are arranged in alternation with and surrounding the bit lines of a second bit line pair; the sense amplifier for the first bit line pair is positioned on one side of the cell array, and the sense amplifier for the second bit line pair is positioned on the other side of the cell array. The sense amplifier connected to either one bit line pair is activated according to the selected word line, the sense amplifier connected to the other bit line pair is kept in the inactive state, and the other bit line pair is kept at the precharge level. Through this configuration, only half the sense amplifier group of conventional devices is activated during reading or writing, so that power consumption can be reduced; moreover, the other bit line pair kept at the precharge level serves the function of shielding the one bit line pair driven by the sense amplifier, so that crosstalk between bit lines is reduced, and the operating margin of the sense amplifier of the one bit line pair can be increased.
In order to achieve these object, another aspect of this invention is a memory circuit having a plurality of memory cells, comprising: a memory cell array, having a plurality of bit line groups each having a first, second, third, and fourth bit line, arranged in order, a first word line group, connected to a pair of memory cells at positions of intersections with a first bit line pair including the first and third bit lines, a second word line group, connected to a pair of memory cells at positions of intersections with a second bit line pair including the second and fourth bit lines;
a first sense amplifier group, positioned on one side of the memory array, and connected to the first bit line pair; and,
a second sense amplifier group, positioned on the other side of the memory array, and connected to the second bit line pair;
wherein complementary data corresponding to a stored data is written to the pair of memory cells from the bit line pair in response to one word line being driven, and moreover, the complementary data stored in the pair of memory cells is read to the bit line pair in response to one word line being driven;
when any one of the word lines of the first word line group is driven, the first sense amplifier group is activated so that the first bit line pair is driven in reverse phase, and the second sense amplifier group is kept in the inactive state so that the second bit line pair is kept at the precharge level; and,
In a preferred embodiment of the above invention, there is further a precharge circuit which precharges the bit line pair to a precharge level; and,
the voltages corresponding to the complementary data written to the pair of memory cells are a first voltage, higher than the precharge level, and a second voltage, lower than the precharge level.
In a still more preferred embodiment, in the above, refresh operations are performed after the first voltage in at least one pair of memory cells has dropped below the precharge level.
In a still more preferred embodiment, in the above, the sense amplifier amplifies one line of the bit line pair to the H level and the other to the L level, and the driving level of the selected word line is set such that the voltage on the H-level side written to the memory cells is lower than the H level of the bit line pair.
In a still more preferred embodiment, in the above, the sense amplifier is activated before the selected word line reaches its driving level, so that the potential of the bit line pair is amplified.